The Indian government has officially notified the Semicon 2.0 scheme with a ₹1.275 trillion budget to build a complete domestic chip ecosystem. The policy offers 40% fiscal support for silicon fabs and 35% for display units, focusing on long-term sustainability. Investors should note the shift toward requiring higher private capital commitments, which aims to filter for serious industrial players.
The Government of India has officially launched the Semicon 2.0 framework, marking the second phase of the country’s strategy to establish a sovereign semiconductor ecosystem. With a total budget outlay of ₹1.275 trillion, the initiative expands on previous efforts by focusing on six key areas, including chip design, manufacturing equipment, wafer fabrication, ATMP (Assembly, Testing, Marking, and Packaging), research and development, and talent training.
The revised policy introduces a more selective approach to fiscal support. To encourage high-quality, large-scale projects, the government has set a 40% fiscal incentive for silicon wafer fabrication facilities that meet a minimum capital investment threshold of ₹20,000 crore. Meanwhile, compound, display, and other specialized semiconductor facilities are eligible for a 35% incentive, provided they commit at least ₹10,000 crore in investment. This structure is intended to ensure that participating firms have the financial stability and technical capability to sustain long-term operations.
For investors and industry observers, the most significant change lies in the stringent eligibility criteria. By requiring high minimum equity commitments, the government is effectively narrowing the field to companies that demonstrate established production capabilities and proven revenue streams. This shift aims to reduce the risk of project failures and ensure that the government's capital is directed toward entities with long-term industrial viability rather than short-term incentives-seeking ventures.
Beyond production capacity, the scheme incorporates a new co-investment model for chip design startups. Instead of relying on traditional grants, the government plans to match private equity funding, allowing startups to scale operations while retaining the potential for future equity buybacks. This is aimed at fostering indigenous intellectual property, which is crucial for reducing dependence on imported technologies.
The program also addresses the need for a specialized workforce, setting a target to train 100,000 additional semiconductor engineers. This builds upon the 85,000 engineers trained during the first phase of the semiconductor mission. A high-level expert panel, co-chaired by the Principal Scientific Adviser and the National Security Adviser, will oversee the identification of strategic chips for targeted support, reflecting the national security dimension of this technology push.
While the policy aims to create a robust domestic supply chain, risks remain that investors should monitor. These include the long gestation periods typical of semiconductor manufacturing, which can strain cash flows for private companies involved. Furthermore, the reliance on global technology partners and the technical challenges of establishing advanced fabrication units by the 2031 target date are hurdles that companies will need to clear. The success of these projects will depend heavily on the ability of private players to execute these capital-intensive plans while managing the cyclical nature of the global chip market.